{"id":1862,"date":"2024-08-14T01:22:23","date_gmt":"2024-08-14T01:22:23","guid":{"rendered":"https:\/\/thepcba.com\/?p=1862"},"modified":"2024-08-14T07:41:10","modified_gmt":"2024-08-14T07:41:10","slug":"pcb-design-for-manufacturability-dfm-best-practices","status":"publish","type":"post","link":"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/","title":{"rendered":"Osv\u011bd\u010den\u00e9 postupy n\u00e1vrhu desek plo\u0161n\u00fdch spoj\u016f pro vyrobitelnost (DFM)"},"content":{"rendered":"<div class=\"row\"  id=\"row-1333944376\">\n\n\t<div id=\"col-2029978842\" class=\"col medium-6 small-12 large-6\"  >\n\t\t\t\t<div class=\"col-inner\"  >\n\t\t\t\n\t\t\t\n<div id=\"ez-toc-container\" class=\"ez-toc-v2_0_82_2 counter-hierarchy ez-toc-counter ez-toc-grey ez-toc-container-direction\">\n<div class=\"ez-toc-title-container\">\n<p class=\"ez-toc-title\" style=\"cursor:inherit\">Obsah<\/p>\n<span class=\"ez-toc-title-toggle\"><a href=\"#\" class=\"ez-toc-pull-right ez-toc-btn ez-toc-btn-xs ez-toc-btn-default ez-toc-toggle\" aria-label=\"P\u0159epnut\u00ed tabulky obsahu\"><span class=\"ez-toc-js-icon-con\"><span class=\"\"><span class=\"eztoc-hide\" style=\"display:none;\">P\u0159ep\u00edna\u010d<\/span><span class=\"ez-toc-icon-toggle-span\"><svg style=\"fill: #999;color:#999\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" class=\"list-377408\" width=\"20px\" height=\"20px\" viewbox=\"0 0 24 24\" fill=\"none\"><path d=\"M6 6H4v2h2V6zm14 0H8v2h12V6zM4 11h2v2H4v-2zm16 0H8v2h12v-2zM4 16h2v2H4v-2zm16 0H8v2h12v-2z\" fill=\"currentColor\"><\/path><\/svg><svg style=\"fill: #999;color:#999\" class=\"arrow-unsorted-368013\" xmlns=\"http:\/\/www.w3.org\/2000\/svg\" width=\"10px\" height=\"10px\" viewbox=\"0 0 24 24\" version=\"1.2\" baseprofile=\"tiny\"><path d=\"M18.2 9.3l-6.2-6.3-6.2 6.3c-.2.2-.3.4-.3.7s.1.5.3.7c.2.2.4.3.7.3h11c.3 0 .5-.1.7-.3.2-.2.3-.5.3-.7s-.1-.5-.3-.7zM5.8 14.7l6.2 6.3 6.2-6.3c.2-.2.3-.5.3-.7s-.1-.5-.3-.7c-.2-.2-.4-.3-.7-.3h-11c-.3 0-.5.1-.7.3-.2.2-.3.5-.3.7s.1.5.3.7z\"\/><\/svg><\/span><\/span><\/span><\/a><\/span><\/div>\n<nav><ul class='ez-toc-list ez-toc-list-level-1' ><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-1\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Introduction\" >\u00davod<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-2\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Understanding_the_Manufacturing_Process\" >Porozum\u011bn\u00ed v\u00fdrobn\u00edmu procesu<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-3\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Utilizing_Standard_Components_and_Materials\" >Vyu\u017eit\u00ed standardn\u00edch sou\u010d\u00e1st\u00ed a materi\u00e1l\u016f<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-4\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Optimizing_PCB_Layout\" >Optimalizace rozvr\u017een\u00ed PCB<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-5\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Incorporating_Design_for_Test_DFT_Techniques\" >Za\u010dlen\u011bn\u00ed technik n\u00e1vrhu pro testov\u00e1n\u00ed (DFT)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-6\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Implementing_Design_for_Assembly_DFA_Techniques\" >Implementace technik n\u00e1vrhu pro mont\u00e1\u017e (DFA)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-7\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Emphasizing_Design_for_Reliability_DFR\" >D\u016fraz na n\u00e1vrh spolehlivosti (DFR)<\/a><\/li><li class='ez-toc-page-1 ez-toc-heading-level-2'><a class=\"ez-toc-link ez-toc-heading-8\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#Conclusion\" >Z\u00e1v\u011br<\/a><ul class='ez-toc-list-level-3' ><li class='ez-toc-heading-level-3'><a class=\"ez-toc-link ez-toc-heading-9\" href=\"https:\/\/thepcba.com\/cs\/pcb-design-for-manufacturability-dfm-best-practices\/#FAQs\" >Nej\u010dast\u011bj\u0161\u00ed dotazy<\/a><\/li><\/ul><\/li><\/ul><\/nav><\/div>\n<h2><span class=\"ez-toc-section\" id=\"Introduction\"><\/span>\u00davod<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>N\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f pro vyrobitelnost (DFM) je d\u016fle\u017eitou sou\u010d\u00e1st\u00ed procesu n\u00e1vrhu desek plo\u0161n\u00fdch spoj\u016f. Tento p\u0159\u00edstup se zam\u011b\u0159uje na vytv\u00e1\u0159en\u00ed desek plo\u0161n\u00fdch spoj\u016f, kter\u00e9 lze snadno a n\u00e1kladov\u011b efektivn\u011b vyr\u00e1b\u011bt, osazovat a testovat. Tento \u010dl\u00e1nek se zab\u00fdv\u00e1 osv\u011bd\u010den\u00fdmi postupy pro DFM, jejich\u017e c\u00edlem je zefektivnit proces n\u00e1vrhu desek plo\u0161n\u00fdch spoj\u016f a zv\u00fd\u0161it celkovou efektivitu a spolehlivost.<\/p>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\n\t\n\n\t<div id=\"col-523449193\" class=\"col medium-6 small-12 large-6\"  >\n\t\t\t\t<div class=\"col-inner\"  >\n\t\t\t\n\t\t\t\n\t<div class=\"img has-hover x md-x lg-x y md-y lg-y\" id=\"image_575714632\">\n\t\t\t\t\t\t\t\t<div class=\"img-inner image-cover dark\" style=\"padding-top:75%;\">\n\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"826\" height=\"555\" src=\"https:\/\/thepcba.com\/wp-content\/uploads\/2024\/08\/8933244.jpg\" class=\"attachment-large size-large\" alt=\"N\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f\" srcset=\"https:\/\/thepcba.com\/wp-content\/uploads\/2024\/08\/8933244.jpg 826w, https:\/\/thepcba.com\/wp-content\/uploads\/2024\/08\/8933244-300x202.jpg 300w, https:\/\/thepcba.com\/wp-content\/uploads\/2024\/08\/8933244-768x516.jpg 768w, https:\/\/thepcba.com\/wp-content\/uploads\/2024\/08\/8933244-18x12.jpg 18w, https:\/\/thepcba.com\/wp-content\/uploads\/2024\/08\/8933244-600x403.jpg 600w\" sizes=\"(max-width: 826px) 100vw, 826px\" \/>\t\t\t\t\t\t\n\t\t\t\t\t<\/div>\n\t\t\t\t\t\t\t\t\n<style>\n#image_575714632 {\n  width: 100%;\n}\n<\/style>\n\t<\/div>\n\t\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\n\t\n<\/div>\n<h2><span class=\"ez-toc-section\" id=\"Understanding_the_Manufacturing_Process\"><\/span>Porozum\u011bn\u00ed v\u00fdrobn\u00edmu procesu<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Z\u00edsk\u00e1n\u00ed p\u0159ehledu o v\u00fdrobn\u00edch schopnostech<\/strong><\/p>\n<p>Z\u00e1kladem \u00fasp\u011b\u0161n\u00e9ho n\u00e1vrhu PCB pro vyrobitelnost je d\u016fkladn\u00e9 pochopen\u00ed v\u00fdrobn\u00edho procesu a mo\u017enost\u00ed v\u00fdrobn\u00edho za\u0159\u00edzen\u00ed. To zahrnuje znalost typ\u016f pou\u017e\u00edvan\u00fdch materi\u00e1l\u016f a technologi\u00ed, jako\u017e i omezen\u00ed a limit\u016f v\u00fdrobn\u00edho procesu. Pochopen\u00edm t\u011bchto faktor\u016f mohou konstrukt\u00e9\u0159i \u010dinit informovan\u00e1 rozhodnut\u00ed, kter\u00e1 zajist\u00ed, \u017ee jejich n\u00e1vrhy desek plo\u0161n\u00fdch spoj\u016f budou optimalizov\u00e1ny pro vyrobitelnost.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Utilizing_Standard_Components_and_Materials\"><\/span>Vyu\u017eit\u00ed standardn\u00edch sou\u010d\u00e1st\u00ed a materi\u00e1l\u016f<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Zjednodu\u0161en\u00ed v\u00fdrobn\u00edho procesu<\/strong><\/p>\n<p>Jedn\u00edm z kl\u00ed\u010dov\u00fdch aspekt\u016f DFM je pou\u017e\u00edv\u00e1n\u00ed standardn\u00edch sou\u010d\u00e1st\u00ed a materi\u00e1l\u016f. Standardizace zjednodu\u0161uje v\u00fdrobn\u00ed proces a m\u016f\u017ee v\u00fdrazn\u011b sn\u00ed\u017eit n\u00e1klady. Nap\u0159\u00edklad pou\u017e\u00edv\u00e1n\u00ed standardn\u00edch rezistor\u016f, kondenz\u00e1tor\u016f a materi\u00e1l\u016f, jako je FR4 nebo FR5, minimalizuje pot\u0159ebu skladovat a spravovat velk\u00e9 mno\u017estv\u00ed jedine\u010dn\u00fdch sou\u010d\u00e1stek, \u010d\u00edm\u017e se sni\u017euje slo\u017eitost v\u00fdroby a n\u00e1klady.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Optimizing_PCB_Layout\"><\/span>Optimalizace rozvr\u017een\u00ed PCB<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Navrhov\u00e1n\u00ed pro snadnou v\u00fdrobu a mont\u00e1\u017e<\/strong><\/p>\n<p>Dob\u0159e optimalizovan\u00e9 uspo\u0159\u00e1d\u00e1n\u00ed desek plo\u0161n\u00fdch spoj\u016f m\u00e1 z\u00e1sadn\u00ed v\u00fdznam pro vyrobitelnost. To zahrnuje minimalizaci po\u010dtu pr\u016fchodek a zjednodu\u0161en\u00ed slo\u017eitosti sm\u011brov\u00e1n\u00ed, co\u017e m\u016f\u017ee usnadnit jednodu\u0161\u0161\u00ed v\u00fdrobn\u00ed proces. Krom\u011b toho m\u016f\u017ee zohledn\u011bn\u00ed tepeln\u00fdch vlastnost\u00ed komponent v uspo\u0159\u00e1d\u00e1n\u00ed zm\u00edrnit tepeln\u00e9 nam\u00e1h\u00e1n\u00ed a potenci\u00e1ln\u00ed po\u0161kozen\u00ed b\u011bhem provozu.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Incorporating_Design_for_Test_DFT_Techniques\"><\/span>Za\u010dlen\u011bn\u00ed technik n\u00e1vrhu pro testov\u00e1n\u00ed (DFT)<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Usnadn\u011bn\u00ed testov\u00e1n\u00ed a lad\u011bn\u00ed<\/strong><\/p>\n<p>Dal\u0161\u00edm d\u016fle\u017eit\u00fdm prvkem DFM je n\u00e1vrh s ohledem na testovatelnost. Za\u010dlen\u011bn\u00ed technik DFT, jako jsou testovac\u00ed body a testovac\u00ed podlo\u017eky, usnad\u0148uje p\u0159\u00edstup k sou\u010d\u00e1stk\u00e1m na desce plo\u0161n\u00fdch spoj\u016f a jejich testov\u00e1n\u00ed. Tento proaktivn\u00ed p\u0159\u00edstup m\u016f\u017ee v\u00fdrazn\u011b zkr\u00e1tit \u010das a sn\u00ed\u017eit n\u00e1klady spojen\u00e9 s testov\u00e1n\u00edm a lad\u011bn\u00edm.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Implementing_Design_for_Assembly_DFA_Techniques\"><\/span>Implementace technik n\u00e1vrhu pro mont\u00e1\u017e (DFA)<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Zjednodu\u0161en\u00ed procesu mont\u00e1\u017ee<\/strong><\/p>\n<p>N\u00e1vrh pro osazov\u00e1n\u00ed (DFA) se zam\u011b\u0159uje na zjednodu\u0161en\u00ed procesu osazov\u00e1n\u00ed desek plo\u0161n\u00fdch spoj\u016f. To zahrnuje pou\u017eit\u00ed sou\u010d\u00e1stek se standardn\u00edmi v\u00fdvody, za\u010dlen\u011bn\u00ed sou\u010d\u00e1stek pro povrchovou mont\u00e1\u017e (SMT) a sn\u00ed\u017een\u00ed po\u010dtu sou\u010d\u00e1stek, kter\u00e9 vy\u017eaduj\u00ed ru\u010dn\u00ed p\u00e1jen\u00ed. Tyto postupy mohou zefektivnit osazov\u00e1n\u00ed a populaci, a t\u00edm zkr\u00e1tit \u010das a sn\u00ed\u017eit n\u00e1klady.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Emphasizing_Design_for_Reliability_DFR\"><\/span>D\u016fraz na n\u00e1vrh spolehlivosti (DFR)<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p><strong>Zaji\u0161t\u011bn\u00ed dlouhodob\u00e9 spolehlivosti a odolnosti<\/strong><\/p>\n<p>Spolehlivost je kl\u00ed\u010dov\u00fdm faktorem p\u0159i DFM. Za\u010dlen\u011bn\u00ed technik n\u00e1vrhu pro spolehlivost (DFR) zahrnuje v\u00fdb\u011br komponent s vysok\u00fdm stupn\u011bm spolehlivosti, pou\u017eit\u00ed \u00fa\u010dinn\u00fdch strategi\u00ed \u0159\u00edzen\u00ed teploty a minimalizaci p\u00e1jec\u00edch spoj\u016f a potenci\u00e1ln\u00edch m\u00edst poruch. Tento p\u0159\u00edstup zaji\u0161\u0165uje, \u017ee desky plo\u0161n\u00fdch spoj\u016f jsou robustn\u00ed a spolehliv\u011b funguj\u00ed po celou dobu sv\u00e9 zam\u00fd\u0161len\u00e9 \u017eivotnosti.<\/p>\n<h2><span class=\"ez-toc-section\" id=\"Conclusion\"><\/span>Z\u00e1v\u011br<span class=\"ez-toc-section-end\"><\/span><\/h2>\n<p>N\u00e1vrh PCB pro vyrobitelnost je kritick\u00fdm aspektem procesu n\u00e1vrhu PCB. Pochopen\u00edm v\u00fdrobn\u00edho procesu, vyu\u017eit\u00edm standardn\u00edch sou\u010d\u00e1stek a materi\u00e1l\u016f, optimalizac\u00ed uspo\u0159\u00e1d\u00e1n\u00ed, za\u010dlen\u011bn\u00edm technik DFT a DFA a d\u016frazem na spolehlivost mohou konstrukt\u00e9\u0159i vytv\u00e1\u0159et desky plo\u0161n\u00fdch spoj\u016f, jejich\u017e v\u00fdroba, osazov\u00e1n\u00ed a testov\u00e1n\u00ed jsou snadn\u00e9 a n\u00e1kladov\u011b efektivn\u00ed. Dodr\u017eov\u00e1n\u00ed t\u011bchto osv\u011bd\u010den\u00fdch postup\u016f nejen zkracuje dobu n\u00e1vrhu a sni\u017euje n\u00e1klady, ale tak\u00e9 zaji\u0161\u0165uje spolehlivou a efektivn\u00ed funkci desek plo\u0161n\u00fdch spoj\u016f po celou dobu jejich \u017eivotnosti.<\/p>\n<hr \/>\n<h3><span class=\"ez-toc-section\" id=\"FAQs\"><\/span>Nej\u010dast\u011bj\u0161\u00ed dotazy<span class=\"ez-toc-section-end\"><\/span><\/h3>\n<p><strong>Ot\u00e1zka: Co je to n\u00e1vrh PCB pro vyrobitelnost (DFM)?<\/strong><br \/>Odpov\u011b\u010f: N\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f pro vyrobitelnost (DFM) je p\u0159\u00edstup k n\u00e1vrhu zam\u011b\u0159en\u00fd na vytv\u00e1\u0159en\u00ed desek plo\u0161n\u00fdch spoj\u016f, kter\u00e9 lze snadno a n\u00e1kladov\u011b efektivn\u011b vyr\u00e1b\u011bt, osazovat a testovat.<\/p>\n<p><strong>Ot\u00e1zka: Pro\u010d je d\u016fle\u017eit\u00e9 pou\u017e\u00edvat p\u0159i n\u00e1vrhu DPS standardn\u00ed sou\u010d\u00e1stky a materi\u00e1ly?<\/strong><br \/>Odpov\u011b\u010f: Pou\u017eit\u00ed standardn\u00edch komponent a materi\u00e1l\u016f zjednodu\u0161uje v\u00fdrobn\u00ed proces, sni\u017euje n\u00e1klady a minimalizuje slo\u017eitost skladov\u00e1n\u00ed a spr\u00e1vy r\u016fzn\u00fdch komponent.<\/p>\n<p><strong>Ot\u00e1zka: Jak p\u0159isp\u00edv\u00e1 optimalizace rozvr\u017een\u00ed DPS k DFM?<\/strong><br \/>Odpov\u011b\u010f: Optimalizace uspo\u0159\u00e1d\u00e1n\u00ed desek plo\u0161n\u00fdch spoj\u016f minimalizac\u00ed pr\u016fchod\u016f, zjednodu\u0161en\u00edm trasov\u00e1n\u00ed a zohledn\u011bn\u00edm tepeln\u00fdch vlastnost\u00ed pom\u00e1h\u00e1 zefektivnit v\u00fdrobn\u00ed proces a sni\u017euje riziko po\u0161kozen\u00ed b\u011bhem provozu.<\/p>\n<p><strong>Ot\u00e1zka: Co jsou techniky DFT (Design for Test)?<\/strong><br \/>Odpov\u011b\u010f: Techniky DFT zahrnuj\u00ed za\u010dlen\u011bn\u00ed prvk\u016f, jako jsou testovac\u00ed body a testovac\u00ed podlo\u017eky, do n\u00e1vrhu desky plo\u0161n\u00fdch spoj\u016f, aby se usnadnil p\u0159\u00edstup k sou\u010d\u00e1stk\u00e1m, jejich testov\u00e1n\u00ed a lad\u011bn\u00ed.<\/p>\n<p><strong>Ot\u00e1zka: K \u010demu slou\u017e\u00ed techniky DFA (Design for Assembly)?<\/strong><br \/>Odpov\u011b\u010f: C\u00edlem technik DFA je zefektivnit proces mont\u00e1\u017ee pou\u017eit\u00edm standardn\u00edch sou\u010d\u00e1stek, technologi\u00ed SMT a omezen\u00edm ru\u010dn\u00edho p\u00e1jen\u00ed sou\u010d\u00e1stek, \u010d\u00edm\u017e se u\u0161et\u0159\u00ed \u010das a sn\u00ed\u017e\u00ed n\u00e1klady.<\/p>\n<p><strong>Ot\u00e1zka: Jak n\u00e1vrh spolehlivosti (DFR) ovliv\u0148uje n\u00e1vrh desek plo\u0161n\u00fdch spoj\u016f?<\/strong><br \/>Odpov\u011b\u010f: Spole\u010dnost DFR se zam\u011b\u0159uje na zaji\u0161t\u011bn\u00ed dlouhodob\u00e9 spolehlivosti a \u017eivotnosti desek plo\u0161n\u00fdch spoj\u016f pou\u017eit\u00edm vysoce spolehliv\u00fdch komponent, \u00fa\u010dinn\u00fdm \u0159\u00edzen\u00edm tepla a minimalizac\u00ed potenci\u00e1ln\u00edch m\u00edst poruch.<\/p>","protected":false},"excerpt":{"rendered":"<p>Pochopen\u00ed v\u00fdrobn\u00edho procesu Z\u00edsk\u00e1n\u00ed p\u0159ehledu o v\u00fdrobn\u00edch mo\u017enostech Z\u00e1kladem \u00fasp\u011b\u0161n\u00e9ho n\u00e1vrhu desek plo\u0161n\u00fdch spoj\u016f pro vyrobitelnost je d\u016fkladn\u00e9 pochopen\u00ed v\u00fdrobn\u00edho procesu a mo\u017enost\u00ed v\u00fdrobn\u00edho za\u0159\u00edzen\u00ed. To zahrnuje znalost typ\u016f pou\u017e\u00edvan\u00fdch materi\u00e1l\u016f a technologi\u00ed, jako\u017e i omezen\u00ed a limit\u016f v\u00fdrobn\u00edho procesu. [...]","protected":false},"author":1,"featured_media":1906,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[1],"tags":[],"_links":{"self":[{"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/posts\/1862"}],"collection":[{"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/comments?post=1862"}],"version-history":[{"count":2,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/posts\/1862\/revisions"}],"predecessor-version":[{"id":1907,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/posts\/1862\/revisions\/1907"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/media\/1906"}],"wp:attachment":[{"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/media?parent=1862"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/categories?post=1862"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/thepcba.com\/cs\/wp-json\/wp\/v2\/tags?post=1862"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}